My PhD Thesis
In this page you may find the abstract of my PhD thesis. Unfortunately, the whole thesis was written in portuguese. However, in the Publications area you may find a series of papers published between 2000 and 2004 that describe the work developed during the PhD preparation.
Thesis submitted to the Faculty of Engineering - University of Porto for examination for the degree of Doctor of Philosophy in Electrical and Computer Engineering in April 2003
Keywords: programmable logic devices, partial and dynamically reconfigurable FPGAs (Field Programmable Gate Arrays), active replication, concurrent structural test, IEEE 1149.1 and IEEE 1532 standards.
Abstract: Reconfigurable logic devices, namely Field Programmable Gate Arrays (FPGAs), experienced a considerable expansion in the last few years, due to an increase in their size and complexity. The introduction of a new type of SRAM based FPGAs, capable of implementing fast run time partial reconfiguration, reinforced the advantages of these devices, wide spreading their usage as a base for reconfigurable computing systems. However, larger dies and smaller submicron scales increase the probability of lifetime operation failures, requiring new test/fault tolerance strategies, capable of assuring long term reliability. This thesis presents a novel non intrusive methodology addressing the concurrent structural test of partial and dynamically reconfigurable FPGAs, based on the active replication and release for test of their internal resources (configurable logic blocks and interconnections). The main objective consists of detecting permanent faults, which may emerge during FPGA operation, and transient faults, such as single event upsets in space environments, which would otherwise become permanent faults. The approach underlying the proposed method assumes that only a relatively small portion of the chip is being tested off line, while the remaining part continues its normal on line operation. If the functionality of a small number of FPGA resources can be relocated on another portion of the same device, in a way that is completely transparent to the operation of the system (i.e. without disturbing the device functionality), then those resources can be taken off line and tested. If no faults are detected, these resources are again made available to be reused; otherwise, they are removed from operation. This fault scanning procedure moves on to relocate and test another set of resources, sweeping through the whole FPGA, systematically testing for faults. The proposed methodology presents a very low overhead at chip level, since all the reconfiguration and test actions are carried out through the IEEE 1149.1 (IEEE Standard Test Access Port and Boundary Scan Architecture) infrastructure.